PXN20RM Datasheet, PDF (879/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
write to A1
Selected Counter Bus ^{and B2}
0x0011FF
0x001000
Match A1
Match A2
write to B2
Match B1
Match A1
Match A2
0x000500
0x000400
0x000000
Output Flip-Flop
FLAG Pin/Register
A1 Value¹
0x000400
B1 Value
B2 Value²
0xxxxxxx 0x001000
0x001000
0x001200
0x001200
A2 Value 0x000500
Notes: 1. EMIOS_CADR[n] = A1
2. EMIOS_CBDR[n] = B2 for write, B1 for read
Figure 28-54. OPWMT with 100% Duty Cycle
Match B1 does not occur
Time
28.4.1.2 Input Programmable Filter (IPF)
The IPF ensures that only valid input pin transitions are received by the unified channel edge detector. A
block diagram of the IPF is shown in Figure 28-55.
The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
IF bits in EMIOS_CCR[n].
FCK
ipg_clk
clk
Prescaled Clock
EMIOSI
Clock
Synchronizer
IF3 IF2 IF1 IF0
5-bit Up Counter
Filter Out
Figure 28-55. lnput Programmable Filter Submodule Diagram
The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing.
If a counter overflow occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector. Figure 28-56
shows a timing diagram of the input filter.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-57