PXN20RM Datasheet, PDF (640/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.5.2.13 Protocol Interrupt Enable Register 0 (PIER0)
Base + 0x001C
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10
11
12
13
R _{FATL INTL ILCF CSA MRC MOC CCL MXS MTX LTXB LTXA TBVB TBVA TI2}
W ^{_IE _IE _IE _IE _IE _IE _IE _IE _IE _IE _IE _IE _IE _IE}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
15
TI1 CYS
_IE _IE
0
0
Figure 26-13. Protocol Interrupt Enable Register 0 (PIER0)
This register defines whether or not the individual interrupt flags defined in the Protocol Interrupt Flag
Register 0 (PIFR0) can generate a protocol interrupt request.
Table 26-19. PIER0 Field Descriptions
Field
FATL_IE
INTL_IE
ILCF_IE
CSA_IE
MRC_IE
MOC_IE
CCL_IE
MXS_IE
MTX_IE
LTXB_IE
Description
Fatal Protocol Error Interrupt Enable — This bit controls FATL_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Internal Protocol Error Interrupt Enable — This bit controls INTL_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Illegal Protocol Configuration Interrupt Enable — This bit controls ILCF_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Cold Start Abort Interrupt Enable — This bit controls CSA_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Missing Rate Correction Interrupt Enable — This bit controls MRC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled.
Missing Offset Correction Interrupt Enable — This bit controls MOC_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Clock Correction Limit Reached Interrupt Enable — This bit controls CCL_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Max Sync Frames Detected Interrupt Enable — This bit controls MXS_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
Media Access Test Symbol Received Interrupt Enable — This bit controls MTX_IF interrupt request
generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
pLatestTx Violation on Channel B Interrupt Enable — This bit controls LTXB_IF interrupt request generation.
0 interrupt request generation disabled.
1 interrupt request generation enabled.
26-26
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor