PXN20RM Datasheet, PDF (950/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Deserial – Serial Peripheral Interface (DSPI)
Table 30-18. DSPI_DSICR Field Descriptions
Field
TSBC
TXSS
CID
DCONT
DSICTAS
Description
Timed Serial Bus Configuration. The TSBC bit enables the Timed Serial Bus configuration. This configuration
allows 32-bit data to be used. It also allows T_DT to be programmable. See Section 30.4.10, Timed Serial Bus
(TSB), for detailed information.
0 Timed Serial Bus configuration disabled.
1 Timed Serial Bus configuration enabled.
If this bit is disabled, the DSPI_DSICR1 register should not be used.
Transmit Data Source Select. The TXSS bit selects the source of data to be serialized. The source can be either
data from host Software written to the DSPI DSI Alternate Serialization Data Register (DSPI_ASDR), or Parallel
Input pin states latched into the DSPI DSI Serialization Data Register (DSPI_SDR).
0 Source of serialized data is the DSPI_SDR.
1 Source of serialized data is the DSPI_ASDR.
Change In Data Transfer Enable. The CID bit enables a change in serialization data to initiate a transfer. The bit
is used in master mode in DSI and CSI configurations to control when to initiate transfers. When the CID bit is
set, serialization is initiated when the current DSI data differs from the previous DSI data shifted out. The
DSPI_COMPR register is compared with the DSPI_SDR or DSPI_ASDR register to detect a change in data.
Refer to Section 30.4.4.5, DSI Transfer Initiation Control, for more information. When the TSBC bit is set, the CID
bit is used for both DSICR and DSICR1 registers.
DSI Continuous Peripheral Chip Select Enable. Enables the PCSx signals to remain asserted between transfers.
The DCONT bit affects the PCS signals in DSI master mode only. See Section 30.4.8.5, Continuous Selection
Format, for details.
0 Return peripheral chip select signals to their inactive state after transfer is complete.
1 Keep peripheral chip select signals asserted after transfer is complete.
DSI Clock and Transfer Attributes Select. The DSICTAS field selects which DSPI_CTARn register is used to
provide transfer attributes in DSI configuration. The DSICTAS field is used in DSI master mode. In DSI slave
mode, the DSPI_CTAR1 is always selected. The table below shows how the DSICTAS values map to the
DSPI_CTARn registers. When TSB configuration is selected the DSICTAS bits control all 32 bits.
DSICTAS
000
001
010
011
DSI Clock and Transfer
Attributes Controlled by
DSPI_CTAR0
DSPI_CTAR1
DSPI_CTAR2
DSPI_CTAR3
DSICTAS
100
101
110
111
DSI Clock and Transfer
Attributes Controlled by
DSPI_CTAR4
DSPI_CTAR5
DSPI_CTAR6
DSPI_CTAR7
DPCSn
DSI Peripheral Chip Select n. The DPCS bits select which PCS signals to assert during a DSI transfer. The DPCS
bits only control the assertions of the PCS signals in DSI master mode.When TSB configuration is enabled, the
DPCS bits only apply for the first 16 bits of the frame; the PCS used for any further bits is selected in the DSICR1
register.
0 Negate PCS[x].
1 Assert PCS[x].
30.3.2.11 DSPI DSI Serialization Data Register (DSPI_SDR)
The DSPI_SDR contains the signal states of the parallel input signals. The pin states of the parallel input
signals are latched into the DSPI_SDR on the rising edge of every system clock. The DSPI_SDR is
read-only. When the TXSS bit in the DSPI_DSICR is negated, the data in the DSPI_SDR is the source of
the serialized data.
30-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor