PXN20RM Datasheet, PDF (756/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.6.17.1 Absolute Timer T1
The absolute timer T1 has the protocol cycle count and the macrotick count as the time base. The timer 1
interrupt flag TI1_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is set at the macrotick start event,
if Equation 26-28 and Equation 26-29 are fulfilled.
Eqn. 26-28
CYCTRCTCCNT & TI1CYSRT1_CYC_MSK = TI1CYSRT1_CYC_VAL & TI1CYSRT1_CYC_MSK
MTCTRMTCT = TI1MTORT1_MTOFFSET
Eqn. 26-29
If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 (PIER0) is asserted,
an interrupt request is generated.
The status bit T1ST is set when the timer is triggered, and is cleared when the timer expires and is
non-repetitive. If the timer expires but is repetitive, the T1ST bit is not cleared and the timer is restarted
immediately. The T1ST is cleared when the timer is stopped.
26.6.17.2 Absolute / Relative Timer T2
The timer T2 can be configured to be an absolute or relative timer by setting the T2_CFG control bit in the
Timer Configuration and Control Register (TICCR). The status bit T2ST is set when the timer is triggered,
and is cleared when the timer expires and is non-repetitive. If the timer expires but is repetitive, the T2ST
bit is not cleared and the timer is restarted immediately. The T2ST is cleared when the timer is stopped.
26.6.17.2.1 Absolute Timer T2
If timer T2 is configured as an absolute timer, it has the same functionality timer T1 but the configuration
from Timer 2 Configuration Register 0 (TI2CR0) and Timer 2 Configuration Register 1 (TI2CR1) is used.
On expiration of timer T2, the interrupt flag TI2_IF in the Protocol Interrupt Flag Register 0 (PIFR0) is
set. If the timer 1 interrupt enable bit TI1_IE in the Protocol Interrupt Enable Register 0 (PIER0) is
asserted, an interrupt request is generated.
26.6.17.2.2 Relative Timer T2
If the timer T2 is configured as a relative timer, the interrupt flag TI2_IF in the Protocol Interrupt Flag
Register 0 (PIFR0) is set, when the programmed amount of macroticks MT[31:0], defined by Timer 2
Configuration Register 0 (TI2CR0) and Timer 2 Configuration Register 1 (TI2CR1), has expired since the
trigger or restart of timer 2. The relative timer is implemented as a down counter and expires when it has
reached 0. At the macrotick start event, the value of MT[31:0] is checked and then decremented. Thus, if
the timer is started with MT[31:0] == 0, it expires at the next macrotick start.
26.6.18 Slot Status Monitoring
The controller provides several means for slot status monitoring. All slot status monitors use the same slot
status vector provided by the PE. The PE provides a slot status vector for each static slot, for each dynamic
slot, for the symbol window, and for the NIT, on a per channel base. The content of the slot status vector
26-142
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor