PXN20RM Datasheet, PDF (902/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
defined: a global mask, used for Rx buffers 0–13 and 16–63, and two extra masks dedicated for buffers 14
and 15. The meaning of each mask bit is the following:
• Mask bit = 0: the corresponding incoming ID bit is “don’t care.”
• Mask bit = 1: the corresponding ID bit is checked against the incoming ID bit, to see if a match
exists.
Note that these masks are used both for standard and extended ID formats. The value of mask registers
should not be changed while in normal operation. Locked frames which had matched a MB through a mask
may be transferred into the MB (upon release) but may no longer match. Table 29-9 shows some examples
of ID masking for standard and extended message buffers.
Table 29-9. Mask Examples for Standard/Extended Message Buffers
Base ID
ID28.................ID18
IDE
Extended ID
ID17......................................ID0
MB2 ID
11111111000
0
MB3 ID
11111111000
1
010101010101010101
MB4 ID
00000011111
0
MB5 ID
00000011101
1
010101010101010101
MB14 ID
11111111000
1
010101010101010101
Rx Global Mask
Rx Msg in¹
Rx Msg in²
Rx Msg in³
Rx Msg in⁴
Rx Msg in⁵
11111111110
11111111001
1
11111111001
0
11111111001
1
01111111000
0
01111111000
1
111111100000000001
010101010101010101
010101010101010100
010101010101010101
Rx 14 Mask
Rx Msg in⁶
Rx Msg in⁷
01111111111
10111111000
1
01111111000
1
111111100000000000
010101010101010101
010101010101010101
1 _{Match for Extended Format (MB3).}
2 _{Match for Standard Format. (MB2).}
3 _{Mismatch for MB3 because of ID0.}
4 _{Mismatch for MB2 because of ID28.}
5 _{Mismatch for MB3 because of ID28, Match for MB14 (uses CANx_RX14MASK).}
6 _{Mismatch for MB14 because of ID27 (uses CANx_RX14MASK).}
7 _{Match for MB14 (uses CANx_RX14MASK).}
Match
3
2
14
14
29.3.4.4.1 Rx Global Mask (CANx_RXGMASK)
This register is provided for legacy support. On the PXN20, setting the BCC bit in CANx_MCR causes
the CANx_RXGMASK Register to have no effect on the module operation.
CANx_RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14–15, which have
individual mask registers. When the FEN bit in CANx_MCR is set (FIFO enabled), the
29-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor