PXN20RM Datasheet, PDF (397/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
The e200z6 core has a 64-bit architectural accumulator register that holds the results of the SPE multiply
accumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependent
fixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The
accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use
them. Instead, they are always copied into a 64-bit destination GPR specified as part of the instruction. The
accumulator however, has to be explicitly cleared when starting a new MAC loop. Based on the type of
instruction, the accumulator can hold either a single 64-bit value or a vector of two 32-bit elements.
13.3.8 12.3.8 Wait Instruction
The z650n3e implements support for the wait instruction. Executing the wait instruction stops
synchronous processor activity. Executing a wait instruction ensures that all instructions have completed
before the wait instruction completes, causes processor instruction fetching to cease, and ensures that no
subsequent instructions are initiated until an interrupt or a debug interrupt occurs. Once the wait instruction
has completed, the program counter will point to the next sequential instruction. The saved value in xSRR0
when the processor re-initiates activity will point to the instruction following the wait instruction.
Execution of a wait instruction places the e200z6 in the “waiting” state. It can be used for power reduction
in a interrupt based system when the core has no processing tasks. An internal output signal from the core
indicates this to the CRP module that the core has entered the waiting state. This is used by the CRP to
place the SOC into low power mode if it has been requested by the user.
When in the “waiting” state, the clock to the core continues to run only if other crossbar masters are active.
13.4 Power Architecture Instruction Extensions – VLE
The variable length encoding (VLE) provides an extension to 32-bit Power Architecture. There are
additional operations defined using an alternate instruction encoding to enable reduced code footprint.
This alternate encoding set is selected on an instruction page basis. A single page attribute bit selects
between standard Power Architecture instruction encodings and VLE instructions for that page of memory.
This page attribute is an extension to the Power Architecture page attributes. Pages can be freely
intermixed, allowing for a mixture of code using both types of encodings.
Instruction encodings in pages marked as using the VLE extension are either 16 or 32 bits long, and are
aligned on 16-bit boundaries. Therefore, all instruction pages marked as VLE are required to use
big-endian byte ordering.
This section describes the various extensions to the Power Architecture instructions that support the VLE
extension.
rfci, rfdi, rfiNot the mask bit 62 of CSRR0, DSRR0, or SRR0 respectively.
The destination address is [D,C]SRR0[32:62] || 0b0.
bclr, bclrl, bcctr, bcctrlNot the mask bit 62 of the LR or CTR respectively.
The destination address is [LR,CTR][32:62] || 0b0.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
13-33