PXN20RM Datasheet, PDF (1184/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Nexus Development Interface (NDI)
Field
EWC
Table 36-21. DC2 Field Descriptions
Description
EVTO Watchpoint Configuration. Any or all of the bits in EWC may be set to configure the EVTO watchpoint.
0000_0000 No Watchpoints trigger EVTO
1xxx_xxxx Watchpoint #0 (IAC1 from Nexus1) triggers EVTO.
x1xx_xxxx Watchpoint #1 (IAC2 from Nexus1) triggers EVTO.
xx1x_xxxx Watchpoint #2 (IAC3 from Nexus1) triggers EVTO.
xxx1_xxxx Watchpoint #3 (IAC4 from Nexus1) triggers EVTO.
xxxx_1xxx Watchpoint #4 (DAC1 from Nexus1) triggers EVTO.
xxxx_x1xx Watchpoint #5 (DAC2 from Nexus1) triggers EVTO.
xxxx_xx1x Watchpoint #6 (DCNT1 from Nexus1) triggers EVTO.
xxxx__xxx1 Watchpoint #7 (DCNT2 from Nexus1) triggers EVTO.
NOTE
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
36.6.8.2 Development Status Register (DS)
The development status register is used to report system debug status. When debug mode is entered or
exited, or an e200z6-defined low-power mode is entered, a debug status message is transmitted with
DS[31:24]. The external tool can read this register at any time. The DS register is shown in Figure 36-16
and its fields are described in Table 36-22.
Nexus Reg: 0x4
Access: User read only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R DBG 0
0
0
LPC
CHK 0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
00000000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
00000000
W
Reset 0
0
0
0
0
0
0
0
00000000
Figure 36-16. Development Status Register (DS)
Table 36-22. DS Field Descriptions
Field
DBG
CPU Debug Mode Status.
0 CPU not in debug mode.
1 CPU in debug mode.
Description
36-34
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor