PXN20RM Datasheet, PDF (499/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Field
MDIS
FRZ
Periodic Interrupt Timer (PIT)
Table 22-3. PITMCR Field Descriptions
Description
Module Disable. This is used to disable the module clock. This bit should be enabled before any other setup is
done.
0 Clock for PIT Timers is enabled.
1 Clock for PIT Timers is disabled (default).
Freeze. Allows the timers to be stopped when the device enters debug mode.
0 Timers continue to run in debug mode.
1 Timers are stopped in debug mode.
22.3.2.2 Timer n Load Value Register (LDVALn)
These registers select the timeout period for the timer interrupts. Changes to this value are visible
immediately.
Offset: Channel_base + 0x0000
LDVAL1 = 0x0100
LDVAL2 = 0x0110
LDVAL3 = 0x0120
LDVAL4 = 0x0130
LDVAL5 = 0x0140
LDVAL6 = 0x0150
LDVAL7 = 0x0160
LDVAL8 = 0x0170
Access: User read/write
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R
TSV31 TSV30 TSV29 TSV28 TSV27 TSV26 TSV25 TSV24 TSV23 TSV22 TSV21 TSV20 TSV19 TSV18 TSV17 TSV16
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22
R
TSV15 TSV14 TSV13 TSV12 TSV11 TSV10 TSV9
W
Reset 0
0
0
0
0
0
0
23
TSV8
0
24
TSV7
0
25
TSV6
0
26
TSV5
0
27
TSV4
0
28
TSV3
0
29
TSV2
0
30
TSV1
0
31
TSV0
0
Figure 22-3. Timer n Load Value Register (LDVALn)
Field
TSVn
Table 22-4. LDVALn Field Descriptions
Description
Time Start Value Bits. These bits set the timer start value. The timer counts down until it reaches 0. Then it
generates an interrupt and loads this register value again. Writing a new value to this register does not restart
the timer. Instead, the value is reloaded once the timer expires. To stop the current cycle and start a timer
period with the new value, the timer must be disabled and enabled again (see Figure 22-8).
22.3.2.3 Timer n Current Value Register (CVALn)
These registers indicate the current timer position.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
22-5