PXN20RM Datasheet, PDF (877/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
typical setup to obtain a trigger with FLAG is enabling DMA and driving the channel’s ipd_done input
high.
A2 is not buffered and therefore its update is immediate. If the channel is running when a change is made
this could cause either the loss of one trigger event or the generation of two trigger events within the same
period. Register A2 can be accessed by reading or writing the eMIOS200 UC Alternate A Register
(EMIOS_ALTA) at UC[n] base address + 0x0014.
FLAG signal is set only at match on the comparator with A2. A match on the comparator with A1 or B1
or B2 has no effect on FLAG.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on A or B respectively. Any FORCMA and/or FORCMB has priority over any
simultaneous match regarding to output pin transitions. Note that the load of B2 content on B1 register at
an A match is not inhibited due to a simultaneous FORCMA/FORCMB assertion. If both FORCMA and
FORCMB are asserted simultaneously the output pin goes to the opposite of EDPOL value such as if A1
and B1 registers had the same value. FORCMA assertion causes the transfer from register B2 to B1 such
as a regular A match, regardless of FORCMB assertion.
If subsequent matches occur on comparators A1 and B, the PWM pulses continue to be generated,
regardless of the state of the FLAG bit.
At OPWMT mode entry the output flip-flop is set to the complement of the EDPOL bit in the
EMIOS_CCR[n] register.
In order to achieve 0% duty cycle both registers A1 and B must be set to the same value. When a
simultaneous match on comparators A and B occur, the output flip-flop is set at every period to the
complement value of EDPOL.
In order to achieve 100% duty cycle the register B1 must be set to a value greater than maximum value of
the selected time base. As a consequence if 100% duty cycle must be implemented the maximum counter
value for the time base is 0xFF_FFFE for a 24-bit counter and respectively 0xFFFE for a 16-bit counter.
When a match on comparator A1 occurs the output flip-flop is set at every period to the value of EDPOL
bit. The transfer from register B2 to B1 is still triggered by the match at comparator A.
As with other eMIOS200 mode, the OPWMT mode implements the Output Disable function. Setting the
ODIS bit in EMIOS_CCR[n] enables the Output Disable function. If the selected Output Disable input
signal is asserted for the channel, the output pin goes to the inverse of the EDPOL. The channel continues
to operate normally, although the output is fixed. When the Output Disable input signal is negated, the
output pin returns to operate as normal.
Figure 28-52 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and
duty cycle update on next period update.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
28-55