PXN20RM Datasheet, PDF (157/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
NOTE
TDO is pulled high on entry into low power mode. It is driven low when the
MCU wakes up.
The assertion of the TDO pin indicates to the debug tool that it can now restore the debug register contents
via the JTAG interface. The Nexus pins cannot be used until the NPC configuration is restored. The TDO
pin remains asserted until the debug tool sets the NPC PCR[SLEEP_SYNC] bit. At that point, TDO is
negated, control of the pin given back to the JTAG controller, and the wakeup interrupt is asserted to the
Z0 and Z6 cores. A block diagram of the SOC blocks and the connections between them to support debug
on sleep wakeup is given in Figure 6-19.
NOTE
The CRP enables only the debug pins that were enabled prior to sleep mode
entry.
16 MHz
IRC
16 MHz IRC
TCK
NPC
TDO
tool handshake
npc_lp_dbg
nexus port enables
sleep reset
nexus pad control
FSM
CRP
debug req
TCLK
debug req
TDO
Pad
Z0 Core
Z6 Core
debug enable
debug enable
TCK
Remaining Nexus & JTAG Pins
TDO
Figure 6-19. Sleep Mode Debug Block Integration
6.4 Real-Time Counter (RTC)
The RTC is a free-running counter used for time-keeping applications. The RTC may be configured to
generate an interrupt at a pre-defined interval independent of the mode of operation. If in sleep mode when
the RTC interval is reached, the RTC first generates a wakeup, and then asserts the interrupt request.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
6-25