PXN20RM Datasheet, PDF (239/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Offset: SIU_BASE + 0x0CA4
Access: User write-only
0
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15
R0
0
0
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0
W
PK_MASK[0:10]
Reset 0
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0
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R0
0
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W
PK[0:10]
Reset 0
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0
0
0
0
Figure 8-53. Masked Parallel GPIO Pin Data Output Register 9 (SIU_MPGPDO9)
8.3.2.46 Masked Serial GPO Register for DSPI_A High (SIU_DSPIAH)
The SIU_DSPIAH register allows any combination of bits in the top half of the 32-bit serialized data frame
from DSPI_A to be updated with a single 32-bit write operation, while allowing other bits to maintain their
previous state. This is accomplished by writing a 16-bit masked value coherently with an update value
contained in a 16-bit output field, and only updating those bits in the output register for which the
corresponding mask bit is set.
Offset: SIU_BASE + 0x0D00
Access: User read/write
0
1
2
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9
10
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15
R _{MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
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R _{DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA}
W ^{31 30 29 28 27 26 25 24 23 222 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-54. Masked Serial GPO Register for DSPI_A High (SIU_DSPIAH)
Table 8-33. SIU_DSPIAH Field Descriptions
Field
Description
MASKn
DATAn
Mask Bit. This bit controls the write access to the corresponding GPO for DSPI_A.
0 The previous value defined by GPO for DSPI_A is maintained.
1 The corresponding GPO for DSPI_A is written with the value defined by the DATAn field.
Pin Data Out. This bit stores the data to be driven out on the GPO for DSPI_A output controlled by this register.
0 Logic low value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
1 Logic high value is driven for the corresponding GPO for DSPI_A when this output is selected in the DSPI
serialization module.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
8-57