PXN20RM Datasheet, PDF (386/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

e200z6 Core (Z6)
match a valid cache tag entry (misses in the cache) or a write access must be written through to memory,
the cache performs a bus cycle on the system bus. Figure 13-13 shows a block diagram of the unified cache
in the e200z6.
Control
Processor
Core
Cache
Control Logic
Data Array
Tag Array
Control
System
Bus
Control
Bus
Interface
Unit
Address/
Data
Data
Address
Data Path
Address Path
Data
Address
Memory
Management
Unit
Figure 13-13. e200z6 Unified Cache Block Diagram
13.3.2.1 Cache Organization
The e200z6 cache is organized as 4 or 8 ways of 128 sets with each line containing 32 bytes (four
doublewords) plus parity of storage. Figure 13-14 illustrates the cache organization, terminology used, the
cache line format, and cache tag formats.
13-22
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor