PXN20RM Datasheet, PDF (590/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
Offset: FEC_BASE + 0x011C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
IADDR2
W
Reset U U U U U U U U U U U U U U U U
16
R
W
Reset U
Field
IADDR2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IADDR2
UUUUUUUUUUUUUUU
Figure 25-17. Descriptor Individual Lower Address (IALR)
Table 25-19. IALR Field Descriptions
Description
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a
unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
25.3.4.17 Descriptor Group Upper Address (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in
the address recognition process for receive frames with a multicast address. This register must be
initialized by the user.
Offset: FEC_BASE + 0x0120
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
GADDR1
W
Reset U U U U U U U U U U U U U U U U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
GADDR1
W
Reset U U U U U U U U U U U U U U U U
Figure 25-18. Descriptor Group Upper Address Register (GAUR)
25-24
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor