PXN20RM Datasheet, PDF (529/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 24-3. EDMA_CR Field Descriptions
Field
CXFR
ECX
GRP1PRI
GRP0PRI
EMLM
CLM
HALT
HOE
ERGA
ERCA
EDBG
Description
Cancel Transfer.
0 Normal operation.
1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to be finished. The
cancel takes effect after the last write of the current read/write sequence. The CXFR bit clears itself after
the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
Error cancel transfer.
0 Normal operation.
1 Cancel the remaining data transfer in the same fashion as the CXFR cancel transfer. Stop the executing
channel and force the minor loop to be finished. The cancel takes effect after the last write of the current
read/write sequence. The ECX bit clears itself after the cancel has been honored. In addition to cancelling
the transfer, the ECX treats the cancel as an error condition; thus updating the EDMA_ESR register and
generating an optional error interrupt. See Section 24.3.2.2, eDMA Error Status Register (EDMA_ESR).
Channel group 1 priority. Group 1 priority level when fixed priority group arbitration is enabled.
Channel group 0 priority. Group 0 priority level when fixed priority group arbitration is enabled.
Enable minor loop mapping.
0 Minor loop mapping disabled. TCD Word 2 is defined as a 32-bit nbytes field.
1 Minor loop mapping enabled. When set, TCDn Word 2 is redefined to include individual enable fields, an
offset field and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to
the source address, the destination address, or both. The NBYTES field is reduced when either offset is
enabled.
Continuous link mode.
0 A minor loop channel link made to itself goes through channel arbitration before being activated again.
1 A minor loop channel link made to itself does not go through channel arbitration before being activated
again. Upon minor loop completion, the channel is active again if that channel has a minor loop channel link
enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next
minor loop.
Halt DMA operations.
0 Normal operation.
1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution
resumes when the HALT bit is cleared.
Halt on error.
0 Normal operation.
1 Any error causes the HALT bit to be set. Subsequently, all service requests are ignored until the HALT bit is
cleared.
Enable round-robin group arbitration.
0 Fixed-priority arbitration is used for selection among the groups.
1 Round-robin arbitration is used for selection among the groups.
Enable Round-Robin Channel Arbitration.
0 Fixed-priority arbitration is used for channel selection within each group.
1 Round-robin arbitration is used for channel selection within each group.
Enable Debug.
0 The assertion of the system debug control input is ignored.
1 The assertion of the system debug control input causes the eDMA to stall the start of a new channel.
Executing channels are allowed to complete. Channel execution resumes when either the system debug
control input is negated or the EDBG bit is cleared.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
24-9