PXN20RM Datasheet, PDF (1008/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Serial Communication Interface (eSCI)
31.3.2.11 eSCI LIN CRC Polynomial Register (eSCI_LPR)
This register provides the CRC polynom for generation and processing of CRC-enhanced LIN frames.
Offset: ESCI_BASE + 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
P
W
Reset 1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
Figure 31-13. eSCI LIN CRC Polynomial Register (eSCI_LPR)
Table 31-13. eSCI_LPR Field Descriptions
Field
Description
Pn Polynomial bit x^Pn. Used to define the LIN polynomial. The standard is x¹⁵ + x¹⁴ + x¹⁰ + x⁸ + x⁷ + x⁴ + x³ + 1 (the
polynomial used for the CAN protocol).
31.3.2.12 eSCI Control Register 3 (eSCI_CR3)
This register is used to control the frame formats and the generation of the ERR bit in the SCI Data Register
(eSCI_SDR).
Offset: ESCI_BASE + 0x001A
0
1
2
3
4
5
6
7
8
9
10
11
R0
0
0
0
0
0
0
SYNM EROE ERFE ERPE M2
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Figure 31-14. eSCI Control Register 1 (eSCI_CR1)
Access: User read/write
12
13
14
15
0
0
0
0
0
0
0
0
Table 31-14. eSCI_CR1 Field Descriptions
Field
SYNM
EROE
ERFE
Description
Synchronization Mode. This bit controls the synchronization mode of the receiver. The synchronization modes
are described in Section 31.4.5.3.14, Bit Synchronization.
0 Synchronization performed at each falling data bit edge.
1 Synchronization performed at start bit qualification only.
ERR flag overrun enable.
0 SCIDRH[ERR] flag not affected by overrun detection.
1 SCIDRH[ERR] flag is set on overrun detection during frame reception.
ERR flag frame error enable.
0 eSCI_SDR[ERR] flag not affected by frame error detection.
1 eSCI_SDR[ERR] flag is set on frame error detection for the data provided in eSCI_SDR.
31-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor