PXN20RM Datasheet, PDF (86/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Signal Description
3.2.1 I/O Power and Ground Segmentation
Table 3-2 gives the preliminary power/ground segmentation. Each segment provides the power and ground
for the I/O pins and can be powered by any voltage within the allowed voltage range regardless of the
power on the other segments. The power/ground segmentation applies regardless of whether a particular
pin is configured for its primary function or GPIO.
Table 3-2. PXN20 Power Segmentation
Pin
Name
Function Description
Voltage¹
Package Pin Locations
208
256
V_DD
V_DDE1
V_DDE2
V_DDE3
V_DDE4
V_DDA
V_DD33
V_DDEMLB
V_DDENEX2
V_RCSEL
V_RC
V_RCCTL
V_DDSYN
V_RH
V_RL
V_SS
Internal Logic Power
1.2 V
D4, D10, H4, G13, K13, N5 D4, D10, H4, G13, K13, N5
External I/O Power
3.3 or 5.0 V
D6
D6
L4
L4
J13
J13
N10
N10
Analog Power
3.3 or 5.0 V
B15
B15
3.3 V I/O Power
3.3 V
L13
L13
Media Local Bus Power
2.5 or 3.3 V
K4
K4
Nexus Power
3.3 V
—
E6, K11, L7
Voltage Regulator Select
V_SSA / V_DDA
H13
H13
Voltage Regulator Control Voltage 3.3 or 5.0 V
B10
B10
Voltage Regulator Control Output
3
—
B11
B11
Clock Synthesizer Power
3.3 V
A12
A12
Analog High Voltage Reference
5.0 V
B16
B16
Analog Low Voltage Reference
0V
C16
C16
Ground
0V
A1, A16, D7, G4, G[7:10], A1, A16, D7, E[7:12], F[7:12],
H[7:10], J[7:10], K[7:10], N13, G4, G[6:12], H[7:12], J[7:12],
T1, T16
K[6:10], K12, L[8:10], L12,
N13, T1, T16
V_SSA
Analog Ground
0V
C15
C15
V_SSSYN
Clock Synthesizer Ground
0V
A15
A15
1 _{Nominal voltages.}
2 _{Dedicated Nexus power pin on 256-pin package only. On the 208-pin package, VDDENEX is tied to VSS internal to the}
package substrate and is not available externally.
3 _{Base current to external NPN power transistor. Voltage may vary.}
3-18
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor