PXN20RM Datasheet, PDF (636/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
Field
RBIF
TBIF
MIE
PRIE
CHIE
WUPIE
FAFBIE
FAFAIE
RBIE
TBIE
Table 26-16. GIFER Field Descriptions (continued)
Description
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSRn[MTD] = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the
corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are asserted. The
application cannot clear this RBIF flag directly. This flag is cleared by the controller when all of the interrupt flags
MBIF of the individual receive message buffers are cleared by the application or if the application has cleared
the interrupt enables bit MBIE.
0 None of the individual receive message buffers has the MBIF and MBIE flag asserted.
1 At least one individual receive message buffer has the MBIF and MBIE flag asserted.
Transmit Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double transmit
message buffers (MBCCSRn[MTD] = 0) both the interrupt flag MBIF and the interrupt enable bit MBIE in the
corresponding Message Buffer Configuration, Control, Status Registers (MBCCSRn) are equal to 1. The
application cannot clear this TBIF flag directly. This flag is cleared by the controller when either all of the
individual interrupt flags MBIF of the individual transmit message buffers are cleared by the application or the
host has cleared the interrupt enables bit MBIE.
0 None of the individual transmit message buffers has the MBIF and MBIE flag asserted.
1 At least one individual transmit message buffer has the MBIF and MBIE flag asserted.
Module Interrupt Enable — This flag controls if the module interrupt line is asserted when the MIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
Protocol Interrupt Enable — This flag controls if the protocol interrupt line is asserted when the PRIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
CHI Interrupt Enable — This flag controls if the CHI interrupt line is asserted when the CHIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
Wakeup Interrupt Enable — This flag controls if the wakeup interrupt line is asserted when the WUPIF flag is
set.
0 Disable interrupt line.
1 Enable interrupt line.
Receive FIFO Channel B Almost Full Interrupt Enable — This flag controls if the FIFO B interrupt line is
asserted when the FAFBIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
Receive FIFO Channel A Almost Full Interrupt Enable — This flag controls if the FIFO A interrupt line is
asserted when the FAFAIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
Receive Buffer Interrupt Enable — This flag controls if the receive buffer interrupt line is asserted when the
RBIF flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
Transmit Interrupt Enable — This flag controls if the transmit buffer interrupt line is asserted when the TBIF
flag is set.
0 Disable interrupt line.
1 Enable interrupt line.
26-22
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor