PXN20RM Datasheet, PDF (795/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Offset: 0x0048 (CCBCR0)
0x0058 (CCBCR1)
0x0068 (CCBCR2)
0x0078 (CCBCR3)
0x0088 (CCBCR4)
0x0098 (CCBCR5)
0x00A8 (CCBCR6)
0x00B8 (CCBCR7)
0x00C8 (CCBCR8)
0x00D8 (CCBCR9)
0x00E8 (CCBCR10)
0x00F8 (CCBCR11)
0x0108 (CCBCR12)
0x0118 (CCBCR13)
0x0128 (CCBCR14)
0x0138 (CCBCR15)
0
1
2
3
4
5
6
7
8
9
10
11
R
BCA[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12
13
14
15
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BFA[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-14. Channel n Current Buffer Configuration Register
Table 27-20. Channel n Current Buffer Configuration Register Field Descriptions
Field
Description
BCA
[15:0]
Buffer Current Address. The BCA field defines a 16-bit address pointer, which identifies the lower half of the
beginning address of the Current Buffer in system memory. The BCA[15:2] bits are loaded from CNBCRn[BSA[15:2]]
when the Next Buffer is ready for processing. This Current Buffer address pointer should always be quadlet aligned
(e.g. BCA[1:0] equals 2’b00). During the processing of the Current Buffer, the BCA field marks which quadlet of the
buffer is currently being processed.
BFA
[15:0]
The upper half of the beginning address of the Current Buffer is system memory is defined by SBCR[SRBA],
ABCA[ARBA], CBCR[CRBA], or IBCR[IRBA] when CECRn[TR] is clear; SBCR[STBA], ABCA[ATBA], CBCR[CTBA],
or IBCR[ITBA] when CECRn[TR] is set, depending on the value of CECRn[CT[1:0]].
Buffer Final Address. The BFA field defines a 16-bit address pointer, which identifies the lower half of the ending
address of the Current Buffer in system memory. The BFA[15:2] bits are loaded from CNBCRn[BEA[15:2]] when the
Next Buffer is read for processing. This Current Buffer address pointer, except when associated with isochronous
channels, should always be quadlet aligned (e.g. BFA[1:0] equals 2’b00). During the processing of the Current Buffer,
the point at which the BCA field becomes equal to (or greater than) the BFA field indicates that the processing of the
Current Buffer ends upon successful completion of the current quadlet (for isochronous and synchronous channels)
or upon successful completion of the current packet (for asynchronous and control channels). It is the responsibility
of system software to ensure the system memory buffers (for RX asynchronous and control channels) can
accommodate overflow in the size of the largest packet supported. Additionally, single-packet buffering can be used
by simply programming CNBCRn[BSA[15:2]] = CNBCRn[BEA[15:2]].
The upper half of the ending address of the Current Buffer in system memory is defined by SBCR[SRBA],
ABCA[ARBA], CBCR[CRBA], and IBCR[IRBA] when CECRn[TR] is clear; SBCR[STBA], ABCA[ATBA],
CBCR[CTBA], or IBCR[ITBA] when CECRn[TR] is set, depending on the value of CECRn[CT[1:0]].
27.3.2.14 Channel n Next Buffer Configuration Register
The Channel n Next Buffer Configuration Register (CNBCRn) allows system software to monitor the
address pointer and buffer length of the Next Buffer in system memory for the logical channel. The
definitions of the bit fields in the CNBCRn register vary depending on the selected channel type.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
27-23