PXN20RM Datasheet, PDF (342/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Offset: FLASH_REGS_BASE + 0x0014
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
0
0
W
HSEL
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-8. High Address Space Block Select Register (HBS)
Table 12-9. HBS Field Descriptions
Field
Description
HSEL[5:0] High Address Space Block Select. High Address Block Select has the same characteristics as LSEL.
12.3.2.7 Address Register (ADR)
The Address register (ADR) provides the first failing address in the event module failures (ECC or
PGM/Erase state machine)
The ADR register is shown in Figure 12-9 and Table 12-10.
Offset: FLASH_REGS_BASE + 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R SAD 0
0
0
0
0
0
0
0
0
0
ADDR
W
Reset 0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ADDR
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
00
0
0
0
0
Figure 12-9. Address Register (ADR)
12-16
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor