PXN20RM Datasheet, PDF (35/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

• Chapter 24, Enhanced Direct Memory Access Controller (eDMA), describes the enhanced DMA
controller implemented on the PXN20.
• Chapter 25, Fast Ethernet Controller (FEC), describes the feature set, operation, and programming
model of the FEC block.
• Chapter 26, FlexRay Communication Controller (FlexRAY), describes the FlexRay
communication controller on the PXN20 that implements the FlexRay Communications System
Protocol Specification, Version 2.1 Rev A.
• Chapter 27, Media Local Bus (MLB), describes the MLB module, a multiplexed bus controller that
transfers multimedia data between the MOST ring and supporting system level ICs.
• Chapter 28, Enhanced Modular Input/Output Subsystem (eMIOS200), describes the eMIOS
module, which provides timed I/O channels for communications with off-chip devices.
• Chapter 29, Controller Area Network (FlexCAN), describes the FlexCAN module, a
communication controller implementing the CAN protocol according to Bosch Specification
version 2.0B and ISO Standard 11898.
• Chapter 30, Deserial – Serial Peripheral Interface (DSPI), describes the DSPI block, which
provides a synchronous serial interface for communication between the PXN20 and external
devices.
• Chapter 31, Enhanced Serial Communication Interface (eSCI), describes the eSCI interface, which
allows asynchronous serial communications with off-chip peripheral devices.
• Chapter 32, Inter-Integrated Circuit Bus Controller Module (I2C), describes the I²C module,
including I²C protocol, clock synchronization, and I²C programming model registers.
• Chapter 33, Cross Triggering Unit (CTU), describes the CTU block, which converts the events
generated by the eMIOS into ADC conversion requests. It also has a PIT channel. The CTU
interfaces between the eMIOS/PIT and the ADC and converts the events generated by the eMIOS
into ADC conversion requests.
• Chapter 34, Analog-to-Digital Converter (ADC), describes the ADC module implemented on the
PXN20.
• Chapter 35, IEEE 1149.1 Test Access Port Controller (JTAGC), describes configuration and
operation of the Joint Test Action Group (JTAG) controller implementation. It describes those
items required by the IEEE 1149.1 standard and provides additional information specific to the
device. For internal details and sample applications, see the IEEE 1149.1 document.
• Chapter 36, Nexus Development Interface (NDI), describes the Nexus Development Interface
(NDI) block, which provides real-time development support capabilities for the PXN20 in
compliance with the IEEE-ISTO 5001-2003 standard.
• Appendix A, Memory Map, provides a detailed listing of the memory-mapped registers for the
PXN20.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about Power Architecture
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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