PXN20RM Datasheet, PDF (939/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Field
PBR
Deserial – Serial Peripheral Interface (DSPI)
Table 30-5. DSPI_CTARn Field Description (continued)
Description
Baud Rate Prescaler. The PBR field selects the prescaler value for the baud rate. This field is only used in master
mode. The baud rate is the frequency of the serial communications clock (SCK). The system clock is divided by
the prescaler value before the baud rate selection takes place. The baud rate prescaler values are listed in the
table below. See the BR[0:3] field description for details on how to compute the baud rate.
PBR
00
01
10
11
Baud Rate Prescaler Value
2
3
5
7
CSSCK
PCS to SCK Delay Scaler. The CSSCK field selects the scaler value for the PCS to SCK delay. This field is only
used in master mode. The PCS to SCK delay is the delay between the assertion of PCS and the first edge of the
SCK. Table 30-8 list the scaler values.The PCS to SCK delay is a multiple of the system clock period and it is
computed according to the following equation:
tCSC
=
------1--------
fSYS

PCSSCK

CSSCK
Eqn. 30-1
See Section 30.4.7.2, PCS to SCK Delay (tCSC), for more details.
ASC
After SCK Delay Scaler. The ASC field selects the scaler value for the after SCK delay. This field is only used in
master mode. The after SCK delay is the delay between the last edge of SCK and the negation of PCS.
Table 30-9 list the scaler values.The after SCK delay is a multiple of the system clock period, and it is computed
according to the following equation:
tASC
=
------1--------
fSYS

PASC

A
SC
Eqn. 30-2
See Section 30.4.7.3, After SCK Delay (tASC), for more details.
DT
Delay after Transfer Scaler. The DT field selects the delay after transfer scaler. This field is only used in master
mode. The delay after transfer is the time between the negation of the PCS signal at the end of a frame and the
assertion of PCS at the beginning of the next frame. Table 30-10 lists the scaler values. In the continuous serial
communications clock operation the DT value is fixed to one TSCK, except when the TSBC bit from DSPI_DSICR
register is enabling the TSB configuration. See detailed information onSection 30.4.10, Timed Serial Bus (TSB).
The delay after transfer is a multiple of the system clock period and it is computed according to the following
equation:
tDT
=
------1--------
fSYS

PDT

DT
See Section 30.4.7.4, Delay after Transfer (tDT), for more details.
Eqn. 30-3
BR
Baud Rate Scaler. The BR field selects the scaler value for the baud rate. This field is only used in master mode.
The pre-scaled system clock is divided by the baud rate scaler to generate the frequency of the SCK. Table 30-11
lists the baud rate scaler values.The baud rate is computed according to the following equation:
SCK baud rate
=
f--S-----Y----S---
PBR

1-----+-----D-----B----R---
BR
Eqn. 30-4
See Section 30.4.7.1, Baud Rate Generator, for more details.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
30-13