PXN20RM Datasheet, PDF (306/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt Vector
0
108
Interrupt
Acknowledge
Read
INTC_IACKR_PCRn
Write
INTC_EOIR_PCRn
INTVEC in
INTC_IACKR_PCRn
0
108
PRI in
INTC_CPR_PCRn
0
1
0
Peripheral Interrupt
Request 100
Figure 10-21. Hardware Vector Mode Handshaking Timing Diagram
10.5 Initialization/Application Information
10.5.1 Initialization Flow
After exiting reset, all of the PRIn and PRC_SELn fields in the INTC priority select registers
(INTC_PSR0–INTC_PSR315) are cleared (set to 0), and PRI in both INTC_CPR_PRC0 and
INTC_CPR_PRC1 is set to 0xF (0b1111). These reset values prevent the INTC from asserting interrupt
requests to the processors. The enable or mask bits in the peripherals are reset such that the peripheral
interrupt requests are negated.
An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an
interrupt request to the processor is:
interrupt_request_initialization:
configure VTES_PRC0,VTES_PRC1,HVEN_PRC0 and HVEN_PRC1 in INTC_MCR
configure VTBA_PRCn in INTC_IACKR_PRCn
raise the PRIn fields and set the PRC_SELx fields to the desired processor in INTC_PSRn_n
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR_PRCn to zero
enable processor(s) recognition of interrupts
10.5.2 Interrupt Exception Handler
These example interrupt exception handlers use Power Architecture assembly code.
10-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor