PXN20RM Datasheet, PDF (558/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
Table 24-22. DMA Request Summary for eDMA (continued)
DMA Request
Channel
Source
DMA_MUX_CHCONFIG9_SOURCE
9
DMA_MUX.CHCONFIG9[SOURCE]
DMA_MUX_CHCONFIG10_SOURCE 10 DMA_MUX.CHCONFIG10[SOURCE]
DMA_MUX_CHCONFIG11_SOURCE 11 DMA_MUX.CHCONFIG11[SOURCE]
DMA_MUX_CHCONFIG12_SOURCE 12 DMA_MUX.CHCONFIG12[SOURCE]
DMA_MUX_CHCONFIG13_SOURCE 13 DMA_MUX.CHCONFIG13[SOURCE]
DMA_MUX_CHCONFIG14_SOURCE 14 DMA_MUX.CHCONFIG14[SOURCE]
DMA_MUX_CHCONFIG15_SOURCE 15 DMA_MUX.CHCONFIG15[SOURCE]
DMA_MUX_CHCONFIG16_SOURCE 16 DMA_MUX.CHCONFIG16[SOURCE]
DMA_MUX_CHCONFIG17_SOURCE 17 DMA_MUX.CHCONFIG17[SOURCE]
DMA_MUX_CHCONFIG18_SOURCE 18 DMA_MUX.CHCONFIG18[SOURCE]
DMA_MUX_CHCONFIG19_SOURCE 19 DMA_MUX.CHCONFIG19[SOURCE]
DMA_MUX_CHCONFIG20_SOURCE 20 DMA_MUX.CHCONFIG20[SOURCE]
DMA_MUX_CHCONFIG21_SOURCE 21 DMA_MUX.CHCONFIG21[SOURCE]
DMA_MUX_CHCONFIG22_SOURCE 22 DMA_MUX.CHCONFIG22[SOURCE]
DMA_MUX_CHCONFIG23_SOURCE 23 DMA_MUX.CHCONFIG23[SOURCE]
DMA_MUX_CHCONFIG24_SOURCE 24 DMA_MUX.CHCONFIG24[SOURCE]
DMA_MUX_CHCONFIG25_SOURCE 25 DMA_MUX.CHCONFIG25[SOURCE]
DMA_MUX_CHCONFIG26_SOURCE 26 DMA_MUX.CHCONFIG26[SOURCE]
DMA_MUX_CHCONFIG27_SOURCE 27 DMA_MUX.CHCONFIG27[SOURCE]
DMA_MUX_CHCONFIG28_SOURCE 28 DMA_MUX.CHCONFIG28[SOURCE]
DMA_MUX_CHCONFIG29_SOURCE 29 DMA_MUX.CHCONFIG29[SOURCE]
DMA_MUX_CHCONFIG30_SOURCE 30 DMA_MUX.CHCONFIG30[SOURCE]
DMA_MUX_CHCONFIG31_SOURCE 31 DMA_MUX.CHCONFIG31[SOURCE]
Description
DMA MUX channel 9 source
DMA MUX channel 10 source
DMA MUX channel 11 source
DMA MUX channel 12 source
DMA MUX channel 13 source
DMA MUX channel 14 source
DMA MUX channel 15 source
DMA MUX channel 16 source
DMA MUX channel 17 source
DMA MUX channel 18 source
DMA MUX channel 19 source
DMA MUX channel 20 source
DMA MUX channel 21 source
DMA MUX channel 22 source
DMA MUX channel 23 source
DMA MUX channel 24 source
DMA MUX channel 25 source
DMA MUX channel 26 source
DMA MUX channel 27 source
DMA MUX channel 28 source
DMA MUX channel 29 source
DMA MUX channel 30 source
DMA MUX channel 31 source
24.5.4 DMA Arbitration Mode Considerations
24.5.4.1 Fixed-Group Arbitration, Fixed-Channel Arbitration
In this mode, the channel service request from the highest priority channel in the highest priority group is
selected to execute. If the eDMA is programmed so the channels within one group use fixed priorities, and
that group is assigned the highest fixed priority of all groups, it is possible for that group to take all the
bandwidth of the eDMA controller. That is, no other groups can be serviced if there is always at least one
DMA request pending on a channel in the highest priority group when the controller arbitrates the next
DMA request. The advantage of this scenario is that latency can be small for channels that need to be
serviced quickly. Preemption is available in this scenario only.
24-38
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor