PXN20RM Datasheet, PDF (430/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

AMBA Crossbar Switch (AXBS)
Table 16-3. AXBS Register Memory Map (continued)
Offset from
AXBS_BASE
(0xFFF0_4000)
Register
Access Reset Value Section/Page
0x0204–0x020F Reserved
0x0210
XBAR_SGPCR2—General-Purpose Control Register, Slave
Port 2
0x0214–0x02FF Reserved
0x0300
XBAR_MPR3—Master Priority Register, Slave Port 3
0x0304–0x030F Reserved
0x0310
XBAR_SGPCR3—General-Purpose Control Register, Slave
Port 3
0x0314–0x05FF Reserved
0x0600
XBAR_MPR6—Master Priority Register, Slave Port 6
0x0604–0x060F Reserved
0x0610
XBAR_SGPCR6—General-Purpose Control Register, Slave
Port 6
0x0614–0x06FF Reserved
0x0700
XBAR_MPR7—Master Priority Register, Slave Port 7
0x0704–0x070F Reserved
0x0710
XBAR_SGPCR7— General-Purpose Control Register, Slave
Port 7
0x0714–0x0EFF Reserved
0x0F00
XBAR_MGPCR7—Master General Purpose Register, Master
Port 7
0x0F04–0x3FFF Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x5400_3210
0x0000_0000
0x5400_3210
0x0000_0000
0x5400_3210
0x0000_0000
0x0000_0000
16.2.1.2/16-6
16.2.1.1/16-4
16.2.1.2/16-6
16.2.1.1/16-4
16.2.1.2/16-6
16.2.1.1/16-4
16.2.1.2/16-6
16.2.1.3/16-8
16.2.1 Register Descriptions
There are two registers for each slave port of the AXBS. The registers can only be accessed in supervisor
mode using 32-bit accesses.
The slave SGPCR also features a bit (RO), which when written with a 1, prevents all slave registers for
that port from being written to again until a reset occurs. The registers remain readable, but future write
attempts have no effect on the registers and are terminated with an error response.
16.2.1.1 Master Priority Registers (XBAR_MPRn)
The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority
mode. They are ignored in round-robin priority mode unless more than one master has been assigned high
priority by a slave.
16-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor