PXN20RM Datasheet, PDF (1255/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Pin
MDO[9]
MDO[10]
MDO[11]
MSEO[0]
MSEO[1]
EVTO
EVTI
Nexus Development Interface (NDI)
Table 36-69. Pin/Pad Multiplexing
Debug Port
Multiplexed?
Available on Available on
208 MPABGA 256 MAPBGA
N2+/3 Aux port
Dedicated
NO
N2+/3 Aux port
Dedicated
NO
N2+/3 Aux port
Dedicated
NO
N2+/3 Aux port
Dedicated
NO
N2+/3 Aux port
Dedicated
NO
N2+/3 Aux port
Dedicated
YES
(could MUX with I/O) (MUX with I/O)
N2+/3Aux port
Dedicated
YES
(could MUX with I/O) (MUX with I/O)
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
Dedicated
The reset and ready pins that are often present as extensions to the JTAG port are not implemented.
Figure 36-81 shows the complete specification for the debug port in terms of pads.
Combined JTAG N2+/3 Port
All packages
256 BGA only
3.3 V Fast Pads
JTAG
Optional
JTAG+
muxed
w/GPIO
(5 V pads)
Aux Nexus 2+/3 port
Figure 36-81. Debug Port Pads
36.10.1 Nexus2+/3 Auxiliary Port
The N2+/3 port provides real-time development class 2+ and class 3 capabilities in compliance with the
IEEE-ISTO 5001-2003 standard. This development support is supplied without requiring external address
and data pins for internal visibility.
The Nexus pads are ready to be used for debug purposes only after the activation of the Nexus controller.
Such activation is consequent to a certain sequence given by the debugger.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
36-105