PXN20RM Datasheet, PDF (521/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 24
Enhanced Direct Memory Access Controller (eDMA)
24.1 Introduction
The enhanced direct memory access controller (eDMA) is a second-generation platform block capable of
performing complex data movements through 32 programmable channels, with minimal intervention from
the host processor. The hardware microarchitecture includes a DMA engine that performs source and
destination address calculations, and the actual data movement operations, along with an SRAM-based
memory containing the transfer control descriptors (TCD) for the channels. This implementation
minimizes the overall block size.
24.1.1 Block Diagram
Figure 24-1 shows a simplified block diagram of the eDMA.
eDMA
SRAM
transfer control descriptor
(TCD)
Slave write address
Slave write data
SRAM
TCD0
eDMA engine
Bus read data
Data path
Bus write data
Bus address
Program model/
channel arbitration
Address
path
Control
TCDn-1*
Slave read data
*n = 32 channels
eDMA Peripheral Request
eDMA Done
Figure 24-1. eDMA Block Diagram
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
24-1