PXN20RM Datasheet, PDF (738/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
26.6.7.1 Message Buffer Cycle Counter Filtering
The message buffer cycle counter filter is a value-mask filter defined by the CCFE, CCFMSK, and
CCFVAL fields in the Message Buffer Cycle Counter Filter Registers (MBCCFRn). This filter determines
a set of communication cycles in which the message buffer is considered for message reception or message
transmission. If the cycle counter filter is disabled (CCFE = 0), this set of cycles consists of all
communication cycles.
If the cycle counter filter of a message buffer does not match a certain communication cycle number, this
message buffer is not considered for message transmission or reception in that communication cycle. In
case of a transmit message buffer assigned to a slot in the static segment, though, this buffer is added to
the matching message buffers to indicate the slot assignment and to trigger the null frame transmission.
The cycle counter filter of a message buffer matches the communication cycle with the number CYCCNT
if at least one of the following conditions evaluates to true:
MBCCFRnCCFE = 0
Eqn. 26-12
CYCCNT & MBCCFRnCCFMSK = MBCCFRnCCFVAL & MBCCFRnCCFMSK
Eqn. 26-13
26.6.7.2 Message Buffer Channel Assignment Consistency
The message buffer channel assignment given by the CHA and CHB bits in the Message Buffer Cycle
Counter Filter Registers (MBCCFRn) defines the channels on which the message buffer will receive or
transmit. The message buffer with number n transmits or receives on channel A if MBCCFRn[CHA] = 1
and transmits or receives on channel B if MBCCFRn[CHB] = 1.
To ensure correct message buffer operation, all message buffers assigned to the same slot and with the
same priority must have a consistent channel assignment. That means they must be either assigned to one
channel only, or must be assigned to both channels. The behavior of the message buffer search is not
defined, if both types of channel assignments occur for one slot and priority. An inconsistent channel
assignment for message buffer 0 and message buffer 1 is depicted in Figure 26-136.
MB0
MB1
MBFIDR0[FID] = 10 MBCCFR0[CHA] = 1, MBCCFR0[CHB] = 0
single channel assignment
MBFIDR1[FID] = 10 MBCCFR1[CHA] = 1, MBCCFR1[CHB] = 1
dual channel assignment
Figure 26-136. Inconsistent Channel Assignment
26.6.7.3 Node Related Slot Multiplexing
The term Node Related Slot Multiplexing applies to the dynamic segment only and refers to the
functionality if there are transmit as well as receive message buffers are configured for the same slot.
According to Table 26-113 the transmit buffer is only found if the cycle counter filter matches, and the
buffer is not locked and committed. In all other cases, the receive buffer will be found. Thus, if the block
has no data to transmit in a dynamic slot, it is able to receive frames on that slot.
26-124
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor