PXN20RM Datasheet, PDF (34/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

• Chapter 6, Clocks, Reset, and Power (CRP), describes the CRP block, which manages entry into,
operation during, and exit from power-saving modes; and maintains all of the control logic that
requires power when other portions of the PXN20 are powered down in power-saving modes.
• Chapter 7, Frequency Modulated Phase-Locked Loop (FMPLL), describes the features and
function of the FMPLL module.
• Chapter 8, System Integration Unit (SIU), describes the SIU module, which controls MCU reset
configuration, pad configuration, external interrupt, general-purpose I/O (GPIO), internal
peripheral multiplexing, and the system reset operation.
• Chapter 9, Boot Assist Module (BAM), describes the BAM, which contains the MCU boot
program code supporting the different booting modes for this device.
• Chapter 10, Interrupts and Interrupt Controller (INTC), summarizes the software and hardware
interrupts for the PXN20 device.
• Chapter 11, General-Purpose Static RAM (SRAM), describes the on-chip static RAM (SRAM)
implementation, covers general operations, configuration, and initialization. It also provides
information and examples of how to minimize power consumption when using the SRAM.
• Chapter 12, Flash Memory Array and Control, describes the flash memory block and the flash
memory controller.
• Chapter 13, e200z6 Core (Z6), describes the organization of the e200z6 Power processor core and
gives an overview of the programming models as they are implemented on the device. The e200z6
is the main processor core on the PXN20.
• Chapter 14, e200z0 Core (Z0), describes the organization of the e200z0 Power processor core and
an overview of the programming models as they are implemented on the device. The e200z0 serves
as an input/output (I/O) processor on the PXN20.
• Chapter 15, Semaphores, describes the module that lets each processor know which processor has
control of common memory.
• Chapter 16, AMBA Crossbar Switch (AXBS), describes the multi-port crossbar switch that
supports simultaneous connections between six master ports and six slave ports.
• Chapter 17, Peripheral Bridge (AIPS-lite), describes the interface between the system bus and
lower bandwidth peripherals.
• Chapter 18, Memory Protection Unit (MPU), describes the block that provides hardware access
control for all memory references generated in the PXN20.
• Chapter 19, Error Correction Status Module (ECSM), describes the ECSM block, which provides
monitoring and control functions to report memory errors and apply error-correcting code (ECC)
implementations.
• Chapter 20, Software Watchdog Timer (SWT), describes a hardware-based timer that can be
implemented to prevent software runaway.
• Chapter 21, System Timer Module (STM), describes the timer control module.
• Chapter 22, Periodic Interrupt Timer (PIT), describes an array of timers that can be used to initiate
interrupts and trigger DMA channels.
• Chapter 23, DMA Channel Multiplexer (DMA_MUX), describes the DMA multiplexer block
implemented on the PXN20.
PXN20 Microcontroller Reference Manual, Rev. 1
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Freescale Semiconductor