PXN20RM Datasheet, PDF (876/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
cycle is varied and must not create glitches. The mode is intended to be used in conjunction with other
channels executing in the same mode and sharing a common timebase. It supports each channel with a
fixed PWM leading edge position with respect to the other channels and the ability to generate a trigger
signal at any point in the period that can be output from the module to initiate activity in other parts of the
device, such as starting ADC conversions.
An external counter driven in either MC Up or MCB Up mode must be selected from one of the counter
buses.
Register A1 defines the leading edge of the PWM output pulse and as such the beginning of the PWM’s
period. This makes it possible to ensure that the leading edge of multiple channels in OPWMT mode can
occur at a specific time with respect to the other channels when using a shared timebase. This can allow
the introduction of a fixed offset for each channel which can be particularly useful in the generation of
lighting PWM control signals where it is desirable that edges are not coincident with each other to help
eliminate noise generation. The value of register A1 represents the shift of the PWM channel with respect
to the selected timebase. A1 can be configured with any value within the range of the selected time base.
Note that registers loaded with 0x00_0000 do not produce matches if the timebase is driven by a channel
in MCB mode.
A1 is not buffered as the shift of a PWM channel must not be modified while the PWM signal is being
generated. In case A1 is modified it is immediately updated and one PWM pulse could be lost.
EMIOS_CBDR[n] address gives access to B2 register for write and B1 register for read. Register B1
defines the trailing edge of the PWM output pulse and as such the duty cycle of the PWM signal. To
synchronize B1 update with the PWM signal and so ensure a correct output pulse generation the transfer
from B2 to B1 is done at every match of register A1. This behavior is the same as the OPWM mode with
next period update.
EMIOS_OUDR register affects transfers between B2 and B1 only.
In order to account for the shift in the leading edge of the waveform defined by register A1, it is necessary
that the trailing edge, held in register B1, can roll over into the next period. This means that a match against
the B1 register should not have to be qualified by a match in the A1 register. The impact of this would
mean that incorrectly setting register B1 to a value less that register A1 results in the output being held
over a cycle boundary until the B1 value is encountered.
This mode provides a buffered update of the trailing edge by updating register B1 with register B2 contents
only at a match of register A1.
The value loaded in register A1 is compared with the value on the selected time base. When a match on
comparator A1 occurs, the output flip-flop is set to the value of the EDPOL bit. When a match occurs on
comparator B, the output flip-flop is set to the complement of the EDPOL bit.
Note that the output pin and flag transitions are based on the posedges of the A1, B1 and A2 match signals.
Please, refer to Figure 28-48 at Section 28.4.1.1.15, Output Pulse Width Modulation with Trigger
(OPWMT) Mode for details on match posedge.
Register A2 defines the generation of a trigger event within the PWM period and A2 should be configured
with any value within the range of the selected time base, otherwise no trigger is generated. A match on
the comparator generates the FLAG signal but it has no effect on the PWM output signal generation. The
28-54
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor