PXN20RM Datasheet, PDF (346/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
Table 12-11. PFCRP0 and PFCRP1 Field Descriptions (continued)
Field
Description
PFLIM[1:0]
PFLASH Prefetch Limit. Controls the prefetch algorithm used by the PFLASH prefetch controller. This field
defines a limit on the maximum number of sequential prefetches that are attempted between buffer misses. In all
situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared by
hardware reset.
00 No prefetching or buffering is performed.
01 The referenced line is prefetched on a buffer miss, i.e., prefetch on miss.
1x the referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if
not already present), i.e., prefetch on miss or hit.
BFEN
PFLASH Line Read Buffers Enable. Enables or disables line read buffer hits. It is also used to invalidate the
buffers. This bit is cleared by hardware reset.
0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers
are successfully filled.
12.3.2.9 Platform Flash Access Protection Register (PFAPR)
Offset: FLASH_REGS_BASE + 0x0024
R
W
Reset
0
1
M7AP
0
0
2
3
M6AP
0
0
4
5
M5AP
0
0
6
7
M4AP
0
0
8
9
M3AP
1
1
10
11
M2AP
1
1
Access: User read/write
12
13
14
15
M1AP
M0AP
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
SHSACC
W
0
0
0
0
SHDACC
0
0
0
0
Reset 1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-11. PFlash Access Protection Register (PFAPR)
Table 12-12. PFlash Access Protection Register (PFAPR) Field Descriptions
Field
M7AP
...
M0AP
Description
Master X Access Protection. These fields are used to control whether read and write accesses to the flash are
allowed based on the master ID of a requesting master.
00 No accesses may be performed by this master.
01 Only read accesses may be performed by this master.
10 Only write accesses may be performed by this master.
11 Both read and write accesses may be performed by this master.
Bit
Bus Master
Bit
Bus Master
M0AP
M1AP
M2AP
M3AP
0 — Z6 Core
1 — Z0 Core
2 — eDMA
3 — reserved
M4AP
M5AP
M6AP
M7AP
4 — FEC
5 — MLB
6 — FlexRay
7 — reserved
12-20
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor