PXN20RM Datasheet, PDF (1143/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
35.4.3.1 Enabling the TAP Controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
35.4.3.2 Selecting an IEEE 1149.1-2001 Register
Access to the JTAGC data registers is achieved by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path is used to read or write the register data by shifting in the data (lsb first) during
the shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting may be terminated after the required number of bits have been
acquired.
35.4.4 JTAGC Instructions
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in Table 35-2. This section gives
an overview of each instruction. Refer to the IEEE 1149.1-2001 standard for more details.
Table 35-2. JTAG Instructions
Instruction
Code[4:0]
Instruction Summary
IDCODE
SAMPLE/PRELOAD
SAMPLE
EXTEST
HIGHZ
CLAMP
ACCESS_AUX_TAP_NPC
ACCESS_AUX_TAP_Z6 (from _ONCE)
ACCESS_AUX_TAP_Z0
ACCESS_AUX_TAP_MULTI
BYPASS
00001
00010
00011
00100
01001
01100
10000
10001
11001
11100
11111
Selects device identification register for shift
Selects boundary scan register for shifting, sampling, and preloading
without disturbing functional operation
Selects boundary scan register for shifting and sampling without
disturbing functional operation
Selects boundary scan register while applying preloaded values to
output pins and asserting functional reset
Selects bypass register while three-stating all output pins and asserting
functional reset
Selects bypass register while applying preloaded values to output pins
and asserting functional reset
Grants the Nexus port controller (NPC) ownership of the TAP
Grants the Nexus e200z6 core interface ownership of the TAP
Grants the Nexus e200z0 core interface ownership of the TAP
Daisy chaining the e200z6 and e200z0 cores—allows instructions to be
clocked into both the e200z0 and e200z6 serially
Selects bypass register for data operations
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
35-9