PXN20RM Datasheet, PDF (905/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
Offset: Base + 0x001C
0
1
2
R0
0
0
W
Reset 0
0
0
16
17
18
R
W
Reset 0
0
0
Access: User read/write
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
19
20
21
22
23
24
25
26
27
28
29
30
31
RXECTR
TXECTR
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 29-9. Error Counter Register (CANx_ECR)
29.3.4.6 Error and Status Register (CANx_ESR)
This register reflects various error conditions, some general status of the device, and it is the source of four
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears bits 16–23. Bits 22–28 are status bits.
Most bits in this register are read-only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT,
which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect).
NOTE
A read clears BIT1_ERR, BIT0_ERR, ACK_ERR, CRC_ERR, FRM_ERR,
and STF_ERR, therefore these bits must not be read speculatively.
Offset: Base + 0x0020
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
R0
0
0
0
0
0
0
0 00 00 0
0
TWRN_ RWRN_
INT INT
W
w1c w1c
Reset 0
0
0
0
0
0
0
0 00 00 0
0
0
0
16
17
18
19
20
21
22
23
24
25
26 27
28
29
30
31
R BIT1_ BIT0_ ACK_ CRC_ FRM_ STF_ TX_ RX_
ERR ERR ERR ERR ERR ERR WRN WRN
IDL
E
TXR
X
FLT_CONF
0
BOFF_ ERR_
INT INT
0
W r1c r1c r1c r1c r1c r1c r1c r1c
w1c w1c
Reset 0
0
0
0
0
0
0
0 00 00 0
0
0
0
Figure 29-10. Error and Status Register (CANx_ESR)
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-21