PXN20RM Datasheet, PDF (1066/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Inter-Integrated Circuit Bus Controller Module (I²C)
Config I²C for
Master TX
CPU writes calling
address to slave
Start
Generated
interrupt
generated
Arb Lost or
No ack?
no
yes _{CPU handles}
condition
CPU sets TX/RX
to RX
CPU: dummy
read of DATAreg
CPU sets
DMAENABLE
Slave TX one
byte of data
ipd_rx_req
generated
no
DMA reads byte
of data
DMA read
(n-2) bytes of
data?
yes
CPU clears
DMA enable
interrupt
generated
interrupt
generated
Stop
generated
CPU reads last
data byte
Slave TX last
data byte
CPU sets
TXACK
CPU reads n-1
data
Slave TX n-1
data byte
Figure 32-15. Flowchart of DMA Mode Master Receive
32.5.2.3 Exiting DMA Mode, System Requirement Considerations
As described above, the final transfers of both Tx and Rx transfers need to be managed via interrupt by the
CPU. To change from DMA to interrupt driven transfers in the I²C module, disable the DMAEN bit in the
IBCR register. The trigger to exit the DMA mode is that the programmed DMA transfer control descriptor
(TCD) has completed all its transfers to/from the I²C module.
32-22
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor