PXN20RM Datasheet, PDF (1138/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
35.1.3.1 Reset
The JTAGC is placed in reset when the TAP controller state machine is in the TEST-LOGIC-RESET state.
The TEST-LOGIC-RESET state is entered upon the assertion of the power-on reset signal, negation of
JCOMP, or through TAP controller state machine transitions controlled by TMS. Asserting power-on reset
or negating JCOMP results in asynchronous entry into the reset state. While in reset, the following actions
occur:
• The TAP controller is forced into the test-logic-reset state, thereby disabling the test logic and
allowing normal operation of the on-chip system logic to continue unhindered.
• The instruction register is loaded with the IDCODE instruction.
In addition, execution of certain instructions can result in assertion of the internal system reset. These
instructions include EXTEST, CLAMP, and HIGHZ.
35.1.3.2 IEEE 1149.1-2001 Defined Test Modes
The JTAGC supports several IEEE 1149.1-2001 defined test modes. The test mode is selected by loading
the appropriate instruction into the instruction register while the JTAGC is enabled. Supported test
instructions include EXTEST, HIGHZ, CLAMP, SAMPLE, and SAMPLE/PRELOAD. Each instruction
defines the set of data registers that may operate and interact with the on-chip system logic while the
instruction is current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE/PRELOAD instructions are active. The single-bit bypass register shift stage is
enabled for serial access between TDI and TDO when the HIGHZ, CLAMP, or reserved instructions are
active. The functionality of each test mode is explained in more detail in Section 35.4.4, JTAGC
Instructions.
35.1.3.3 Bypass Mode
When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass
mode. While in bypass mode, the single-bit bypass shift register is used to provide a minimum-length
serial path to shift data between TDI and TDO.
35.1.3.4 TAP Sharing Mode
There are three selectable auxiliary TAP controllers that share the TAP with the JTAGC. Selectable TAP
controllers include the Nexus port controller (NPC), e200z6 OnCE, and e200z0. The instructions required
to grant ownership of the TAP to the auxiliary TAP controllers are ACCESS_AUX_TAP_NPC,
ACCESS_AUX_TAP_Z6 (from _ONCE) (for e200z6), and ACCESS_AUX_TAP_Z0. Additionally, the
instruction for daisy chaining the e200z6 and e200z0 is ACCESS_AUX_TAP_MULTI (allows
instructions to be clocked into both the e200z0 and e200z6 serially). Instruction opcodes for each
instruction are shown in Table 35-2.
When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is transferred to the
selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any
35-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor