PXN20RM Datasheet, PDF (481/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Software Watchdog Timer (SWT)
Offset: SWT_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{MAP MAP MAP MAP MAP MAP MAP MAP} 0
0
0
0
0
0
0
0
W0
1
2
3
4
5
6
7
Reset 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0
0
0
KEY RIA WND ITR HLK SLK
FRZ WEN
W
Reset 0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
Figure 20-1. SWT Control Register (SWT_CR)
Table 20-2. SWT_CR Field Descriptions
Field
MAPn
Description
Master Access Protection for Master n. The PXN20 bus master assignments are shown in the following table.
0 Access for the master is not enabled
1 Access for the master is enabled.
KEY
RIA
WND
ITR
HLK
Bit
MAP0
MAP1
MAP2
MAP3
Bus Master
0 — Z6 Core
1 — Z0 Core
2 — eDMA
3 — not used
Bit
MAP4
MAP5
MAP6
MAP7
Bus Master
4 — FEC
5 — MLB
6 — FlexRay
7 — not used
Keyed Service Mode.
0 Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog.
1 Keyed Service Mode, two pseudorandom key values are used to service the watchdog.
Reset on Invalid Access.
0 Invalid access to the SWT generates a bus error.
1 Invalid access to the SWT causes a system reset if WEN = 1.
Window Mode.
0 Regular mode, service sequence can be done at any time.
1 Windowed mode, the service sequence is only valid when the down counter is less than the value in the
SWT_WN register.
Interrupt Then Reset.
0 Generate a reset on a time-out.
1 Generate an interrupt on an initial time-out, reset on a second consecutive time-out.
Hard Lock. This bit is only cleared at reset.
0 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read/write registers if SLK = 0.
1 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read-only registers.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
20-3