PXN20RM Datasheet, PDF (189/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Integration Unit (SIU)
Table 8-1. SIU Memory Map (continued)
Offset from
SIU_BASE
(0xFFFE_8000)
Register
0x0D18
SIU_DSPIDH—Masked serial GPO register for DSPI_D high
0x0D1C
SIU_DSPIDL—Masked serial GPO register for DSPI_D low
0x0D20–0x0D43 Reserved
0x0D44
SIU_EMIOSA—eMIOS select register for DSPI_A
0x0D48
SIU_DSPIAHLA—SIU_DSPIAH/L select register for DSPI_A
0x0D4C–0x0D53 Reserved
0x0D54
SIU_EMIOSB—eMIOS select register for DSPI_B
0x0D58
SIU_DSPIBHLB—SIU_DSPIBH/L select register for DSPI_B
0x0D5C–0x0D63 Reserved
0x0D64
SIU_EMIOSC—eMIOS select register for DSPI_C
0x0D68
SIU_DSPICHLC—H/L select register for DSPI_C
0x0D6C–0x0D73 Reserved
0x0D74
SIU_EMIOSD—eMIOS select register for DSPI_D
0x0D78–0x0D7B SIU_DSPIDHLD—SIU_DSPIDH/L select register for DSPI_D
0x0D7C–0x3FFF Reserved
1 _{See register description for reset value.}
Access Reset Value Section/Page
R/W 0x0000_0000 8.3.2.52/8-61
R/W 0x0000_0000 8.3.2.53/8-62
R/W 0x0000_0000 8.3.2.54/8-62
R/W 0x0000_0000 8.3.2.55/8-63
R/W 0x0000_0000 8.3.2.56/8-64
R/W 0x0000_0000 8.3.2.57/8-64
R/W 0x0000_0000 8.3.2.58/8-65
R/W 0x0000_0000 8.3.2.59/8-65
R/W 0x0000_0000 8.3.2.60/8-66
R/W 0x0000_0000 8.3.2.61/8-67
Table 8-2 provides absolute hex addresses for the SIU_PCR and SIU_GPDO registers.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
8-7