PXN20RM Datasheet, PDF (702/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
SADR_MBHF = (i * 10) + SYMBADR[SMBA]; (0 < i < 1024)
3. The message buffer header fields for each FIFO have to be a contiguous area.
Eqn. 26-9
26.6.4.4 Message Buffer Header Area (MCR[FAM] = 1)
The message buffer header area contains all message buffer header fields of the physical message buffers
for the individual message buffers and receiver shadow buffers. The following rules apply to the message
buffer header fields for the two type of message buffers.
1. The start address SADR_MBHF of each message buffer header field for individual message
buffers and receive shadow buffers must fulfill Equation 26-10.
SADR_MBHF = (i * 10) + SYMBADR[SMBA]; (0 < i < 256)
Eqn. 26-10
26.6.4.5 FIFO Message Buffer Header Area (MCR[FAM] = 1)
The FIFO message buffer header area contains all message buffer header fields of the physical message
buffers for the FIFO. The following rules apply to the FIFO message buffer header fields.
1. The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill
Equation 26-11.
SADR_MBHF = (i * 10) + RFSYMBADR[SMBA]; (0 < i < 1024)
2. The message buffer header fields for each FIFO have to be a contiguous area.
Eqn. 26-11
26.6.4.6 Message Buffer Data Area
The message buffer data area contains all the message buffer data fields of the physical message buffers.
Each message buffer data field must start at a 16-bit boundary.
26.6.4.7 Sync Frame Table Area
The sync frame table area is used to provide a copy of the internal sync frame tables for application access.
Refer to Section 26.6.12, Sync Frame ID and Sync Frame Deviation Tables, for the description of the sync
frame table area.
26.6.5 Physical Message Buffer Description
This section provides a detailed description of the usage and the content of the two parts of a physical
message buffer, the message buffer header field and the message buffer data field.
26.6.5.1 Message Buffer Protection and Data Consistency
The physical message buffers are located in the FlexRay memory. The controller provides no means to
protect the FlexRay memory from uncontrolled or illegal host or other client write access. To ensure data
consistency of the physical message buffers, the application must follow the write access scheme that is
given in the description of each of the physical message buffer fields.
26-88
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor