PXN20RM Datasheet, PDF (991/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Chapter 31
Enhanced Serial Communication Interface (eSCI)
31.1 Introduction
The eSCI allows asynchronous serial communications with peripheral devices and other CPUs. The eSCI
has special features that allow the eSCI to operate as a LIN bus master, complying with the LIN 1.3, 2.0,
2.1, and SAE J2602 specification.
31.1.1 Block Diagram
A simplified block diagram of the eSCI illustrates the functionality and interdependence of major blocks
(see Figure 31-1).
DMA
CTRL
Internal Data Bus
RX DMA
Channel
Receive
Data Register
RXD
BUS
CLK
Polarity
Control
Baud Rate
Generator
RCLK
LIN FSM
Control
Receive
Shift Register
Receive
Control
Wakeup
Control
Frame Format
Control
Loop
Control
Interrupt
Generation
CPU
IRQ
16
TCLK
Transmit
Control
DMA
Control
TX DMA
Channel
Transmit
Shift Register
Transmit
Data Register
TXD
Internal Data Bus
Figure 31-1. eSCI Block Diagram
31.1.2 Features
The eSCI has these major features:
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
31-1