PXN20RM Datasheet, PDF (792/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Media Local Bus (MLB)
Offset: 0x0044 (CSCR0)
0x0054 (CSCR1)
0x0064 (CSCR2)
0x0074 (CSCR3)
0x0084 (CSCR4)
0x0094 (CSCR5)
0x00A4 (CSCR6)
0x00B4 (CSCR7)
0x00C4 (CSCR8)
0x00D4 (CSCR9)
0x00E4 (CSCR10)
0x00F4 (CSCR11)
0x0104 (CSCR12)
0x0114 (CSCR13)
0x0124 (CSCR14)
0x0134 (CSCR15)
0
1
2
3
4
5
6
7
8
9
10
11
R BM BF 0
0
0
0
0
0
0
0
0
0
W
Reset 1
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12
13
IVB[1:0]
14
15
GIRB/
GB
RDY
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0 PBS PBD PBDB PBPE 0 LFS HBE BE CBS CBD CBDB CBPE
W
w1c w1c w1c w1c
w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-13. Channel n Status Configuration Register
Table 27-19. Channel n Status Configuration Register Field Descriptions
Field
Description
BM Buffer Empty. When set, the local channel buffer (for channel n) is empty. This bit is set and cleared by hardware. At
reset, the local channel buffer is empty (BM = 1).
0 Buffer not empty.
1 Buffer empty.
BF Buffer Full. When set, the local channel buffer (for channel n) is full. This bit is set and cleared by hardware.
0 Buffer not full.
1 Buffer full.
IVB[1:0]
Isochronous Valid Bytes. These bits are loaded by hardware with the number of valid bytes in the last packet of a
broken Isochronous RX channel. Used in conjunction with CCBCRn[BCA], IVB[1:0] can be used by software to
determine the final valid byte of the local channel buffer. This field is only valid for logical channels configured for
isochronous RX data.
00 Final valid byte = (CCBCRn[BCA] – 5).
01 Final valid byte = (CCBCRn[BCA] – 4).
10 Final valid byte = (CCBCRn[BCA] – 3).
11 Final valid byte = (CCBCRn[BCA] – 2).
GIRB
Generate Isochronous Receive Break. When set, this bit causes hardware to terminate the current packet, flush the
local channel buffer, clear the RDY bit, and load IVB[1:0]. This bit is set by system software and cleared by hardware.
This field is only valid for logical channels configured for isochronous RX data.
0 Do not generate isochronous receive break.
1 Generate isochronous receive break.
GB Generate Break. When the local channel buffer is configured for TX data, the setting of this bit causes hardware to
send the AsyncBreak (26h) or ControlBreak (36h) command and stop the transfer. When the local channel buffer is
configured for RX data, the setting of this bit causes hardware to send the MediaLB RxStatus ReceiverBreak (70h)
and stop the transfer. This bit is set by system software and cleared by hardware. This bit is only valid for logical
channels configured for asynchronous or control data.
0 Do not generate break.
1 Generate break.
27-20
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor