PXN20RM Datasheet, PDF (167/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
Table 7-2. SYNSR Register Field Descriptions (continued)
Field
Description
CALDONE
Calibration Complete. The CALDONE bit is an indication of whether the calibration sequence has been
completed since the last time modulation was enabled. If CALDONE = 0 then the calibration sequence is in
progress or modulation is disabled. If CALDONE = 1 then the calibration sequence has been completed, and
frequency modulation is operating.
0 Calibration not complete.
1 Calibration complete.
CALPASS
Calibration Passed. The CALPASS bit tells whether the calibration routine was successful. If CALPASS = 1 and
CALDONE = 1 then the routine was successful. If CALPASS = 0 and CALDONE = 1, then the routine was
unsuccessful. When the calibration routine is initiated the CALPASS is asserted. CALPASS remains asserted
until modulation is disabled by clearing the EDEPTH bits in the ESYNCR2 register or a failure occurs within the
FMPLL calibration sequence.
0 Calibration unsuccessful,
1 Calibration successful.
If calibration is unsuccessful, then actual depth is not guaranteed to match the desired depth
MODE
0
1
1
1
Table 7-3. System Clock Status Per Mode
PLLSEL
X
0
1
1
PLLREF
X
0
0
1
Clock Mode
PLL Off mode
Reserved
Normal PLL mode with external clock reference
Normal PLL mode with crystal clock reference
NOTE
If LOLF has been set previously (due to an unexpected loss of lock
condition) and then cleared (by writing a 1), a change of the MFD, PREDIV
or DEPTH fields can cause the LOLF to be set again which can trigger an
interrupt request if LOLIRQ bit is set. In addition, changing the RATE bit
will also set the LOLF regardless of previous conditions.
The Loss of Lock Interrupt Request enable in the Synthesizer Control
Register (FMPLL_SYNCR[LOLIRQ]) should be cleared before any
change to the multiplication factor (MFD), PREDIV, modulation depth
(DEPTH), or modulation rate (RATE) to avoid unintentional interrupt
requests. After the PLL has locked (LOCK=1), LOLF should be cleared (by
writing a 1) and LOLIRQ may be set again if required.
7.3.2.2 FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
This is one of two FMPLL synthesizer control registers that are used to access enhanced features in the
FMPLL. The bit fields in the ESYNCR1 behave as described in Figure 7-3.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
7-5