PXN20RM Datasheet, PDF (155/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Clocks, Reset, and Power (CRP)
6.3.4.1 Sleep Mode Reset Operation
The reset controller in the SIU controls the normal reset sequences from POR, LVI, and other resets when
the device is in RUN mode. The CRP controls reset operation for the device in sleep mode.
The external RESET pin is enabled in all modes. Assertion of the RESET pin or a POR during sleep mode
causes the device to restart in RUN mode.
Upon power up from sleep mode, POR and reset is asserted to all logic that was powered down. The SIU
processes the sleep recovery POR in the same manner as a normal POR. The RSR[PORS] bit in the SIU
is set after the reset controller sequence completes. The CRP_PSCR[SLEEPF] bit is set in this case to
indicate that the POR came from a sleep recovery.
NOTE
When powering up from sleep mode, the BOOTCFG pin is not read and the
BAM boot sequence is bypassed since the Z6 and Z0 cores branch to the
appropriate reset vector set in the CRP_Z0VEC and CRP_Z6VEC registers,
assuming the core was active (not held in reset) prior to sleep mode entry.
6.3.5 Low-Power Wakeup
A POR, LVI12, or assertion of the external RESET pin causes exit from sleep mode as a reset condition,
and not a wakeup. A POR or external reset is captured in the SIU Reset Status Register. All CRP registers
are reset for a POR, but some like the CRP_RTCC are maintained for an external reset. Note that there are
no internal reset sources (except POR and LVI12) active in sleep.
There are four methods for waking up the device from sleep mode:
• RTC counter match
• RTC counter rollover
• API counter match
• External pin transition
All wakeup methods are independently enabled. The RTC, RTC rollover, and API wakeup logic is
discussed in Section 6.4, Real-Time Counter (RTC).
Wakeup from sleep can be enabled from transitions on as many as 32 external pins. External pin wakeup
source selection is done in the CRP_PWKENH/L registers. To be used as a low-power mode wakeup, pins
must be configured with the output buffer disabled in the SIU_PCR registers prior to entry into the
low-power mode. During sleep mode, all pins (except the 32 wakeup pins and RESET) are put into a safe
state with the input buffer, output buffer, and pull devices disabled. The wakeup pins input buffer enables
will retain the state configured prior to entry into sleep mode with the output buffers and pull devices
disabled.
External pin wakeup generation can be selected for either a rising edge event on the pin, falling edge, or
both. The edge capture logic can be selectively clocked from either the 16 MHz IRC clock for faster
wakeup, or the 128 kHz IRC clock for lower average power. For wakeup, the value of the Pin Assignment
(PA) bitfield in the SIU_PCR does not matter. This enables a pin, such as a CAN receive pin, to wake up
the device on a transition.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
6-23