PXN20RM Datasheet, PDF (127/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

System Clock Description
NOTE
The CLKOUT provides a nominal 50% duty cycle clock with the exception
of the case when the CLKOUT prescaler is equal to ÷ 1 and the system clock
and has been divided by its prescaler. When running at this full speed
(116 MHz system clock), the CLKOUT should be configured by the user
with a divide ratio of at least ÷ 4.
Out of Reset the CLKOUT pin is disabled to minimize noise. This must be
turned on by the user during initialization.
5.3.4 Nexus Message Clock (MCKO) Divider
The Nexus message clock (MCKO) divider can be programmed to divide the system clock by 1, 2, 4, or
8, based on the MCKO_DIV bit field in the port configuration register (PCR) in the Nexus port controller
(NPC). The reset value of MCKO_DIV selects an MCKO clock frequency one half of the system clock
frequency. The MCKO divider is configured by writing to the NPC through the JTAG port. The
MCKO_EN bit may be used to disable the MCKO clock. The MCKO_GT bit may be used to disable the
MCKO clock when Nexus is not actively transmitting messages on the Nexus port.
NOTE
The MCKO provides a nominal 50% duty cycle clock with the exception of
the case that the MCKO prescaler is equal to ÷ 1 and the system clock has
been divided by its prescaler. There is no guaranteed phase relationship
between CLKOUT and MCKO.
NOTE
Z6 tracing is supported for MCKO divides of 1, 2, 4, or 8. Since the Z0
clocking is based on half the system bus clock frequency, the Z0 tracing is
supported for MCKO divides of 2, 4, or 8 with a divide of 1 not supported.
Also, concurrent tracing of both the Z6 and Z0 is supported for MCKO
divides of 2, 4, or 8, with a divide of 1 not supported.
5.3.5 Peripheral Clock Dividers
The system and peripheral bus clocks can all be divided down to tune performance to meet the needs of
the application, helping to save power and to meet the required peripheral speeds. The system clock speed
can be divided down from ÷ 1 to ÷ 16 in discrete steps (÷ 1, ÷ 2, ÷ 4, ÷ 8, ÷ 16). This allows the CPU speed
to be reduced to 1 MHz when operating from the 16 MHz IRC for slow dynamic run current. In addition
the peripherals can divide this system bus clock speed for their normal operation from ÷ 1 to ÷ 8 in discrete
steps (÷ 1, ÷ 2, ÷ 4, ÷ 8) enabling slow peripheral groups such as Peripheral Set 1 (Refer to Table 5-1 for
more information) to be able to be optimized to run at more efficient speeds.
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
5-9