PXN20RM Datasheet, PDF (1048/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Inter-Integrated Circuit Bus Controller Module (I²C)
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• Basic DMA interface
Features currently not supported:
• No support for general call address
• Not compliant to ten-bit addressing
32.1.4 Modes of Operation
There are two operating modes of the I²C module: run mode and halt mode. In run mode, I²C_x = 0 in the
SIU_HLT0 register and all functional parts of the I²C module are running. In halt mode, I²C_x = 1 in the
SIU_HLT0 register and all clocks to the I²C module are disabled.
32.2 External Signal Description
Refer to Chapter 3, Signal Description, for detailed signal descriptions.
32.3 Memory Map and Registers
This section provides a detailed description of all I²C registers.
32.3.1 Module Memory Map
Table 32-1 shows the I²C memory map. The address of each register is given as an offset to the I²C base
address. Registers are listed in address order, identified by complete name and mnemonic.
Table 32-1. I²C Memory Map
Offset from
I²C_BASE
I²C_A = 0xFFF8_8000
I²C_B = 0xFFF8_C000
I²C_C = 0xC3F8_8000
I²C_D = 0xC3F8_C000
Register
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
IBAD—I²C bus address register
IBFD—I²C bus frequency divider register
IBCR—I²C bus control register
IBSR—I²C bus status register
IBDR—I²C bus data I/O register
IBIC—I²C bus interrupt configuration register
0x0006–0x3FFF
Reserved
Access Reset Value Section/Page
R/W
0x00
32.3.2.1/32-5
R/W
0x00
32.3.2.2/32-5
R/W
0x80
32.3.2.3/32-8
R/W
0x80
32.3.2.4/32-9
R/W
0x00
32.3.2.5/32-10
R/W
0x00
32.3.2.6/32-11
32-4
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor