PXN20RM Datasheet, PDF (917/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Controller Area Network (FlexCAN)
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide
which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration
process, the data of that MB may no longer be coherent, therefore deactivation of that MB is done.
Even with the coherence mechanism described above, writing to the control and status word of active MBs
when not in freeze mode may produce undesirable results. Examples are:
• Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no
re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is
deactivated during the matching process after it was scanned, then this MB is marked as invalid to
receive the frame, and FlexCAN keeps looking for another matching MB within the ones it has not
scanned yet. If it cannot find one, then the message is lost. Suppose, for example, that two MBs
have a matching ID to a received frame, and the user deactivated the first matching MB after
FlexCAN has scanned the second. The received frame is lost even if the second matching MB was
free to receive.
• If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then FlexCAN
looks for another winner within the MBs that it has not scanned yet. Therefore, it may transmit an
MB with ID that may not be the lowest at the time because a lower ID might be present in one of
the MBs that it had already scanned before the deactivation.
• There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end
of move-out). After this point, it is transmitted but no interrupt is issued and the code field is not
updated. In order to avoid this situation, the abort procedures described in Section 29.4.5.1,
Transmission Abort Mechanism, should be used.
29.4.5.3 Message Buffer Lock Mechanism
Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When
the CPU reads the Control and Status word of an “active not empty” Rx MB, FlexCAN assumes that the
CPU wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.
The lock is released when the CPU reads the free-running timer (global unlock operation), or when it reads
the Control and Status word of another MB. The MB locking is done to prevent a new frame to be written
into the MB while the CPU is reading it.
NOTE
The locking mechanism only applies to Rx MBs which have a code different
than INACTIVE (‘0000’) or EMPTY¹ (‘0100’). Also, Tx MBs cannot be
locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the array are
programmed with the same ID, and FlexCAN has already received and stored messages into these two
MBs. Suppose now that the CPU decides to read MB number 5 and at the same time another message with
the same ID is arriving. When the CPU reads the control and status word of MB number 5, this MB is
locked. The new message arrives and the matching algorithm finds out that there are no free to receive
MBs, so it decides to override MB number 5. However, this MB is locked, so the new message cannot be
written there. It remains in the SMB waiting for the MB to be unlocked, and not written to the MB until
1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior is honored when the
BCC bit is negated.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
29-33