PXN20RM Datasheet, PDF (540/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, software must clear the appropriate bit, negating the
interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this
purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears
the corresponding channel’s interrupt request. A 0 in any bit position has no effect on the corresponding
channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single
channel can be cleared without performing a read-modify-write sequence to the EDMA_IRQRL.
Offset: EDMA_BASE + 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
19
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-14. eDMA Interrupt Request Register (EDMA_IRQRL)
Table 24-15. EDMA_IRQRL Field Descriptions
Field
INTn
Description
eDMA Interrupt Request n.
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
24.3.2.14 eDMA Error Register (EDMA_ERL)
The EDMA_ERL provides a bit map for the 32 channels signaling the presence of an error for each
channel. EDMA_ERL maps to channels 31–0.
The DMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across
32 channels to form an error interrupt request, which is then routed to the interrupt controller. During the
execution of the interrupt service routine associated with any eDMA errors, it is software’s responsibility
to clear the appropriate bit, negating the error interrupt request. Typically, a write to the EDMA_CER in
the interrupt service routine is used for this purpose. The normal eDMA channel completion indicators,
setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not
affected when an error is detected.
24-20
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor