PXN20RM Datasheet, PDF (363/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Flash Memory Array and Control
done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that in
the event of an aborted margin read, the MISR registers contain a signature for the portion of the
operation that was completed prior to the abort, but it is not deterministic.
7. Wait until the UT0[AID] bit goes high.
8. Read values in the MISR registers (UM0 through UM4) to ensure correct signature.
9. Write a logic 0 to the UT0[AIE] bit.
12.4.2.3 ECC Logic Check
ECC logic can be checked by providing data to be read in the UT0[DSI], UT1[DAI] and/or UT2[DAI]
registers. Then array reads can be done, ensuring expected results. The ECC logic check consists of the
following sequence of events:
1. Enable UTest mode.
2. Write UT0[EIE] to 1.
3. Write UT0[DSI], UT1[DAI], and/or UT2[DAI] bits to provide data and check bit values to be read.
Single- or double-bit detections/corrections can be simulated by properly choosing data and check
bit combinations.
4. Write double word address to receive the data input in step 3 into the ADR register.
12.4.3 Flash Shadow Block
The flash shadow block is a memory-mapped block in the flash memory map. Program and erase of the
shadow block are enabled when MCR[PEAS] = 1 only. After the user has begun an erase operation on the
shadow block, the operation cannot be suspended to program the main address space and vice-versa. The
user must terminate the shadow erase operation to program or erase the main address space.
NOTE
If an erase of user space is requested, and a suspend is done with attempts
to erase suspend program shadow space, this attempted program is directed
to user space as dictated by the state of MCR[PEAS]. Likewise an attempted
erase suspended program of user space, while the shadow space is being
erased, is directed to shadow space as dictated by the state of MCR[PEAS].
The shadow block cannot use the RWW feature. After an operation is started in the shadow block, a read
cannot be done to the shadow block, or any other block. Likewise, after an operation is started in a block
in low-/mid-/high-address space, a read cannot be done in the shadow block.
The shadow block contains information about how the lock registers are reset. The first and second words
can be used for reset configuration words. All other words can be used for user-defined functions or other
configuration words.
The shadow block may be locked/unlocked against program or erase by using the LML or SLL discussed
in Section 12.3.2, Register Descriptions.
Programming the shadow row has similar restrictions to programming the array in terms of how ECC is
calculated. See Section 12.4.1.3, Flash Programming, for more information. Only one program is allowed
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
12-37