PXN20RM Datasheet, PDF (866/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
MODE[6] = 1
Cycle n
Write to A2
Internal Counter Match A1
Cycle n + 1
Cycle n + 2
Match A1
Write to B2
Match B1
Match B1
Write to A2
Match B1
0x000008
0x000006
0x000004
0x000002
0x000001
Due to B1 Match
Cycle n – 1
Output Pin
FLAG Set Event
Output Disable
A1 Value 0x000002
0x000004
0x000006
A2 Value 0x000002 0x000004
0x000006
B1 Value 0x000008
0x000006
B2 Value 0x000008
0x000006
EDPOL = 0
Figure 28-42. OPWFMB Mode with Active Output Disable
Time
The output disable has a synchronous operation, meaning that the assertion of the output disable input pin
causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the output
disable input is deasserted the output pin transition at the following A1 or B1 match.
In Figure 28-42 it is assumed that the output disable input is enabled and selected for the channel. Refer
to Section 28.3.2.8, eMIOS200 Control Register (EMIOS_CCR[n]), for a description of how the ODIS
and ODISSL bits enable and select the output disable inputs.
The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on comparators A or B respectively. Similar to a B1 match FORCMB sets the
internal counter to 0x00_0001. The FLAG bit is not set by the FORCMA or FORCMB bits being asserted.
Figure 28-43 shows the generation of 100% and 0% duty cycle signals. It is assumed EDPOL = 0 and the
resultant prescaler value is 1. Initially, A1 = 0x00_0008 and B1 = 0x00_0008. In this case, the B1 match
has precedence over the A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This
cycle corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value
greater or equal to B1.
28-44
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor