PXN20RM Datasheet, PDF (302/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Interrupts and Interrupt Controller (INTC)
The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
10.4.1.3 Unique Vector for Each Interrupt Request Source
Each peripheral and software settable interrupt request is assigned a hardwired unique 9-bit vector.
Software settable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt requests
are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests.
10.4.2 Priority Management
The asserted interrupt requests are compared to each other based on their PRIn and PRC_SELn values set
in the INTC priority select registers (INTC_PSR0 –INTC_PSR315). The result of that comparison is
compared to PRI in the associated current priority register (INTC_CPR_PRC0 or INTC_CPR_PRC1). The
results of those comparisons are used to manage the priority of the ISR being executed by the associated
processor. The associated LIFO also assists in managing that priority.
10.4.2.1 Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator submodules shown in Figure 10-1 are used to
compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted
peripheral or software settable interrupt request is higher than the current priority for a given processor,
then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral
or software settable interrupt request is generated for the associated INTC interrupt acknowledge register
(INTC_IACKR_PRC0 or INTC_IACKR_PRC1) and, if in hardware vector mode, for the interrupt vector
provided to the processor.
10.4.2.1.1 Priority Arbitrator Submodule
The priority arbitrator submodule for each processor compares all the priorities of all of the asserted
interrupt requests assigned to that processor, both peripheral and software settable. The output of the
priority arbitrator submodule is the highest of those priorities assigned to a given processor. Also, any
interrupt requests which have this highest priority are output as asserted interrupt requests to the associated
request selector submodule.
10.4.2.1.2 Request Selector Submodule
If only one interrupt request from the associated priority arbitrator submodule is asserted, then it is passed
as asserted to the associated vector encoder submodule. If multiple interrupt requests from the associated
priority arbitrator submodule are asserted, only the one with the lowest vector passes as asserted to the
associated vector encoder submodule. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software settable interrupt requests.
10.4.2.1.3 Vector Encoder Submodule
The vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from the
request selector submodule for the associated processor.
10-34
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor