PXN20RM Datasheet, PDF (600/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Fast Ethernet Controller (FEC)
• The FEC software driver ensures that the Ready bit cleared in at least
one TxBD.
• Every frame uses more than one TxBD and every TxBD but the last is
written back immediately after the data is fetched.
• The FEC software driver ensures a minimum frame size, n. The
minimum number of TxBDs is then rounded up to the nearest integer
(although the result cannot be less than 3). The default Tx FIFO size is
192 Bytes; this size is programmable.
25.4.7 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it starts processing receive
frames immediately. When FEC_RX_DV asserts, the receiver first checks for a valid PA/SFD header. If
the PA/SFD is valid, it is stripped and the frame processed by the receiver. If a valid PA/SFD is not found,
the frame is ignored.
In serial mode, the first 16 bit times of FEC_RXD0 following assertion of FEC_RX_DV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence
is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data
sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected,
the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA.
If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified
to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which
indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See Section 25.4.14.2, Reception
Errors, for more details.
Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the EIMR register. A
receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed
the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the receive buffer
descriptor (RxBD) is set. See Section 25.5.2, Ethernet Receive Buffer Descriptor (RxBD), for more
details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT
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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor