PXN20RM Datasheet, PDF (671/1376 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

FlexRay Communication Controller (FlexRAY)
Base + 0x00E8
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[31:16]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-51. Receive FIFO System Memory Base Address High Register (RFSYMBADHR)
Base + 0x00EA
Write: Disabled Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SMBA[15:4]
W
0
0
0
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-52. Receive FIFO System Memory Base Address Low Register (RFSYMBADLR)
These registers define the system memory base address for the receive FIFO if the FIFO address mode bit
MCR[FAM] is set to 1. The system memory base address is used by the BMIF to calculate the physical
memory address for system memory accesses for the FIFOs.
Table 26-60. RFSYMBADR Field Descriptions
Field
SMBA
Description
System Memory Base Address — This is the value of the system memory base address for the receive FIFO
if the FIFO address mode bit MCR[FAM] is set to 1. It is defines as a byte address.
26.5.2.52 Receive FIFO Periodic Timer Register (RFPTR)
Base + 0x00EC
0
1
R0
0
W
Reset 0
0
2
3
4
5
6
7
8
9
10
11
12
PTD
0
0
0
0
0
0
0
0
0
0
0
Figure 26-53. Receive FIFO Periodic Timer Register (RFPTR)
Write: POC:config
13
14
15
0
0
0
This register holds periodic timer duration for the periodic FIFO timer. The periodic timer applies to both
FIFOs (see Section 26.6.9.3, FIFO Periodic Timer).
Table 26-61. RFPTIR Field Descriptions
Field
PTD
Description
Periodic Timer Duration — This value defines the periodic timer duration in terms of macroticks.
0000 Timer stays expired.
3FFF Timer never expires.
other Timer expires after specified number of macroticks, expires and is restarted at each cycle start.
Freescale Semiconductor
PXN20 Microcontroller Reference Manual, Rev. 1
26-57